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cy7c138 4k x 8/9 dual-port static ram with sem, int, busy cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06037 rev. *g revised december 2, 2010 features true dual-ported memory cells that enable simultaneous reads of the same memory location 4k x 8 organization (cy7c138) 0.65-micron complementary metal oxide semiconductor (cmos) for optimum speed and power high speed access: 25 ns low operating power: i cc = 160 ma (max.) fully asynchronous operation automatic power-down transistor transistor logic (ttl) compatible expandable data bus to 32 bits or more using master/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to-port communication available in 68-pin plastic leaded chip carrier (plcc) pb-free packages available functional description the cy7c138 is a high speed cmos 4k x 8 dual-port static ram. various arbitration schem es are included on the cy7c138 to handle situations when multiple processors access the same piece of data. two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. the cy7c138 can be used as a standalone 8-bit dual-port static ram or multiple devices can be combined to function as a 16-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 16-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multiprocessor des igns, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semap hore) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power-down feature is controlled independently on each port by a chip enable (ce ) pin or sem pin. r/w l ce l oe l a 11l a 0l a 0r a 11r r/w r ce r oe r i/o 7l i/o 0l i/o 7r i/o 0r interrupt semaphore arbitration control i/o control i/o memory array address decoder address decoder sem l sem r busy l busy r int l int r m/s [2] [2] [1, 2] [1, 2] r/w l ce l oe l r/w r ce r oe r logic block diagram notes 1. busy is an output in master mode and an input in slave mode. 2. interrupt: push-pull output and requires no pull-up resistor. [+] feedback
cy7c138 document #: 38-06037 rev. *g page 2 of 21 contents pin configurations ........................................................... 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ....................................................................... 5 switching characteristics................................................. 5 architecture .................................................................... 14 functional description ................................................... 14 write operation ......................................................... 14 read operation ......................................................... 14 interrupts ................................................................... 14 busy .......................................................................... 14 master/slave ............................................................. 14 semaphore operation ............................................... 14 ordering information ...................................................... 17 4k x8 dual-port sram .............................................. 17 ordering code definition .... ....................................... 17 package diagram ............................................................ 18 acronyms ........................................................................ 19 document conventions ................................................. 19 units of measure ....................................................... 19 document history page ................................................. 20 sales, solutions, and legal information ...................... 21 worldwide sales and design s upport ......... .............. 21 products .................................................................... 21 psoc solutions ......................................................... 21 \ [+] feedback
cy7c138 document #: 38-06037 rev. *g page 3 of 21 pin configurations figure 1. 68-pin plcc (top view) table 1. pin definitions left port right port description i/o 0l?7l i/o 0r?7r data bus input/output a 0l?11l a 0r?11r address lines ce l ce r chip enable oe l oe r output enable r/w l r/w r read/write enable sem l sem r semaphore enable. when asserted low, allows access to eight semaphores. the three least significant bits of the address lines will determine which semaphore to write or read. the i/o 0 pin is used when writing to a semaphore. semaphores are requested by writing a 0 into the respective location. int l int r interrupt flag. int l is set when right port writes location ffe and is cleared when left port reads location ffe. int r is set when left port writes location fff and is cleared when right port reads location fff. busy l busy r busy flag m/s master or slave select v cc power gnd ground 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 67 60 59 58 57 56 55 54 53 52 51 50 49 48 3132 33 34 35 36 37 38 39 40 41 42 43 5 4 3 2 168 666564636261 a a 4l a 3l a 2l a 1l a 0l int l busy l gnd m/s busy r int r a 0r i/o 2l i/o 3l i/o 4l i/o 5l gnd i/o 6l i/o 7l v cc gnd i/o 0r i/o 1r i/o 2r v cc a 2728 29 30 98 7 6 47 46 45 44 a 1r a 2r a 3r a 4r i/o 3r i/o 4r i/o 5r i/o 6r 25 26 6l 7l a 8l a 9l a a 10l 11l v cc nc nc ce l sem l r/w l oe l nc i/o i/o 1l 0l a a 6r 7r a 8r a 9r a 10r nc nc ce r sem r r/w r oe r i/o 7r gnd a 11r a 5r a 5l nc cy7c138 nc nc table 2. selection guide description 7c138-25 unit maximum access time (ns) 25 ns maximum operating current commercial 180 ma maximum standby current for i sb1 commercial 40 ma [+] feedback
cy7c138 document #: 38-06037 rev. *g page 4 of 21 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. [3] storage temperature ................................ ?65 ? c to +150 ?? c ambient temperature with power applied ........................................... ?55 ?? c to +125 ?? c supply voltage to ground potenti al ...............?0.5 v to +7.0 v dc voltage applied to outputs in high z state ..............................................?0.5 v to +7.0 v dc input voltage [4] ........................................?0.5 v to +7.0 v output current into outputs (low) .............................. 20 ma static discharge voltage........................................... >2001 v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 5 v 10% industrial ?40 ? c to +85 ? c 5 v 10% electrical characteristics over the operating range parameter description test conditions 7c138-25 unit min max v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min., i ol = 4.0 ma ? 0.4 v v ih 2.2 ? v v il input low voltage ? 0.8 v i ix input leakage current gnd < v i < v cc ?10 +10 ? a i oz output leakage current output disabled, gnd < v o < v cc ?10 +10 ? a i cc operating current v cc = max., i out = 0 ma, outputs disabled commercial ? 180 ma industrial ? 190 i sb1 standby current (both ports ttl levels) ce l and ce r > v ih , f = f max [5] commercial ? 40 ma industrial ? 50 i sb2 standby current (one port ttl level) ce l and ce r > v ih , f = f max [5] commercial ? 110 ma industrial ? 120 i sb3 standby current (both ports cmos levels) both ports ce and ce r > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0 [5] commercial ? 15 ma industrial ? 30 i sb4 standby current (one port cmos level) one port ce l or ce r > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, active port outputs, f = f max [5] commercial ? 100 ma industrial ? 115 notes 3. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 4. pulse width < 20 ns. 5. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 [+] feedback
cy7c138 document #: 38-06037 rev. *g page 5 of 21 capacitance [6] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 10 pf c out output capacitance 15 pf figure 2. ac test loads and waveforms switching characteristics over the operating range [7] parameter description 7c138-25 unit min max read cycle t rc read cycle time 25 ? ns t aa address to data valid ? 25 ns t oha output hold from address change 3 ? ns t ace ce low to data valid ? 25 ns t doe oe low to data valid ? 15 ns t lzoe [8,9,10] oe low to low z 3 ? ns t hzoe [8,9,10] oe high to high z ? 15 ns t lzce [8,9,10] ce low to low z 3 ? ns t hzce [8,9,10] ce high to high z ? 15 ns t pu [10] ce low to power-up 0 ? ns t pd [10] ce high to power-down ? 25 ns write cycle t wc write cycle time 25 ? ns t sce ce low to write end 20 ? ns notes 6. tested initially and after any design or proc ess changes that may affect these parameters. 7. test conditions assume signal transition time of 3 ns or less, ti ming reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i oi /i oh and 30-pf load capacitance. 8. at any temperature and voltage condition for any device, t hzce is less than t lzce and t hzoe is less than t lzoe . 9. test conditions used are load 3 10. this parameter is guaranteed but not tested. 3.0 v gnd 90% 90% 10% < 3ns < 3 ns 10% all input pulses (a) normal load (load 1) r1 = 893 ? 5 v output r2 = 347 ? c= 30 pf r th = 250 ? v th = 1.4 v output c = 30pf (b) th venin equivalent (load 1) (c) three-state delay (load 3) c = 30 pf output load (load 2) r1 = 893 ? r2 = 347 ? 5v output c= 5pf [+] feedback
cy7c138 document #: 38-06037 rev. *g page 6 of 21 t aw address setup to write end 20 ? ns t ha address hold from write end 2 ? ns t sa address setup to write start 0 ? ns t pwe write pulse width 20 ? ns t sd data setup to write end 15 ? ns t hd data hold from write end 0 ? ns t hzwe [11,12] r/w low to high z ? 15 ns t lzwe [11,12] r/w high to low z 3 ? ns t wdd [13] write pulse to data delay ? 50 ns t ddd [13] write data valid to read data valid ? 30 ns busy timing [14] t bla busy low from address match ? 20 ns t bha busy high from address mismatch ? 20 ns t blc busy low from ce low ? 20 ns t bhc busy high from ce high ? 20 ns t ps port setup for priority 5 ? ns t wb r/w low after busy low 0 ? ns t wh r/w high after busy high 20 ? ns t bdd [15] busy high to data valid ? note 15 ns interrupt timing [14] t ins int set time ? 25 ns t inr int reset time ? 25 ns semaphore timing t sop sem flag update pulse (oe or sem ) 10 ? ns t swrd sem flag write to read time 5 ? ns t sps sem flag contention window 5 ? ns notes 11. test conditions used are load 3. 12. this parameter is guaranteed but not tested. 13. for information on part-to-part delay through ram cells from writing port to reading port, refer to read timing with port-to -port delay waveform. 14. test conditions used are load 2. 15. t bdd is a calculated parameter and is the greater of t wdd ? t pwe (actual) or t ddd ? t sd (actual). switching characteristics over the operating range [7] (continued) parameter description 7c138-25 unit min max [+] feedback
cy7c138 document #: 38-06037 rev. *g page 7 of 21 switching waveforms figure 3. read cycle no. 1 (either port address access) [16, 17] t rc t aa t oha data valid previous data valid data out address notes 16. r/w is high for read cycle. 17. device is continuously selected ce = low and oe = low. this waveform cannot be used for semaphore reads [+] feedback
cy7c138 document #: 38-06037 rev. *g page 8 of 21 figure 4. read cycle no. 2 (either port ce /oe access) [18, 19, 20, 21] figure 5. read timing with port-to-p ort delay (m/s = l) [22, 23] switching waveforms (continued) t ace t lzoe t doe t hzoe t hzce data valid data out sem or ce oe t lzce t pu i cc i sb t pd valid t ddd t wdd match match r/w r data inr data outl t wc address r t pwe valid t sd t hd address l notes 18. r/w is high for read cycle. 19. device is continuously selected ce = low and oe = low. this waveform cannot be used for semaphore reads. 20. address valid prior to or coincident with ce transition low. 21. ce l = l, sem = h when accessing ram. ce = h, sem = l when accessing semaphores. 22. busy = high for the writing port. 23. ce l = ce r = low. [+] feedback
cy7c138 document #: 38-06037 rev. *g page 9 of 21 figure 6. write cycle no. 1: oe three-states data i/os (either port) [24, 25, 26] figure 7. write cycle no. 2: r/w three-states data i/os (either port) [24, 26, 27] switching waveforms (continued) t aw t wc data valid high impedance t sce t sa t pwe t hd t sd t ha t hzoe t lzoe sem or ce r/w oe data out data in address t aw t wc t sce t sa t pwe t hd t sd t hzwe t ha high impedance sem or ce r/w data out data in t lzwe data valid address notes 24. the internal write time of the memory is defined by the overlap of ce or sem low and r/w low. both signals must be low to initiate a write, and either signal can terminate a write by going high. the data input setup and hold ti ming should be referenced to the rising edge of the signal tha t terminates the write. 25. if oe is low during a r/w controlled write cycle, t he write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during a r/w controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified t pwe . 26. r/w must be high during all address transitions. 27. data i/o pins enter high impedance when oe is held low during write. [+] feedback
cy7c138 document #: 38-06037 rev. *g page 10 of 21 figure 8. semaphore read after write timing, either side [28] figure 9. timing diagra m of semaphore contention [29, 30, 31] switching waveforms (continued) t sop t aa sem r/w oe i/o 0 valid address valid address t hd data in valid data out valid t oha a 0 ?a 2 t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle match t sps a 0l ?a 2l match r/w l sem l a 0r ?a 2r r/w r sem r notes 28. ce = high for the duration of the above timing (both write and read cycle). 29. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high 30. semaphores are reset (available to both ports) at cycle start. 31. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will con trol the semaphore. [+] feedback
cy7c138 document #: 38-06037 rev. *g page 11 of 21 figure 10. timing diagram of read with busy (m/s = high) [32] figure 11. write timing with busy input (m/s =low) switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l t pwe r/w busy t wb t wh note 32. ce l = ce r = low. [+] feedback
cy7c138 document #: 38-06037 rev. *g page 12 of 21 figure 12. busy timing diagram no. 1 (ce arbitration) [33] figure 13. busy timing diagram no. 2 (address arbitration) [33] note 33. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc address l,r busy r ce l ce r busy l ce r ce l address l,r ce l valid first: ce r valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r left address valid first: right address valid first: [+] feedback
cy7c138 document #: 38-06037 rev. *g page 13 of 21 figure 14. interrupt timing diagrams notes 34. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 35. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) write fff t wc t ha read fff t rc t inr write ffe t wc read ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins left side sets int r : right side clears int r : right side sets int l : left side clears int l : [34] [34] [35] [35] [35] [35] [+] feedback
cy7c138 document #: 38-06037 rev. *g page 14 of 21 architecture the cy7c138 consists of an array of 4k words of 8 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes and reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be used for port?to?port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the cy7c138 can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the cy7c138 has an automatic power-down feature controlled by ce . each port is provided with its own output enable control (oe ), which enables data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a vali d write. a writ e operation is controlled by either the oe pin (see write cycle no. 1 waveform) or the r/w pin (see write cycle no . 2 waveform). data can be written to the device t hzoe after the oe is deasserted or t hzwe after the falling edge of r/w . required inputs for non-contention operations are summarized in table 3 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; otherwise the data read is not deterministic. data is valid on the port t ddd after the data is presen ted on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data is available t ace after ce or t doe after oe is asserted. if the user of the cy7c138 wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin. interrupts the interrupt flag (int ) permits communications between ports.when the left port writes to location fff, the right port?s interrupt flag (int r ) is set. this flag is cleared when the right port reads that same location. settin g the left port?s interrupt flag (int l ) is accomplished when the righ t port writes to location ffe. this flag is cleared when the left port reads location ffe. the message at fff or ffe is user-defined. see table 4 for input requirements for int . int r and int l are push-pull outputs and do not require pull-up resistors to operate. busy l and busy r in master mode are push-pull outputs and do not require pull-up resistors to operate. busy the cy7c138 provides on-chip arbitration to alleviate simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other the busy logic determines which port has access. if t ps is violated, one port definitely gains permission to the location, but it is not guaranteed which one. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this enables the device to interface to a master device with no external components.writing of slave devices must be delayed until after the busy input has settled. otherwis e, the slave chip may begin a write cycle during a contention si tuation.when pr esented as a high input, the m/s pin allows the device to be used as a master and therefore the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c138 provides eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports.the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value is available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes control over the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of t he a semaphore.if the left side no longer requires the semaphore, a 1 is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip enable for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other addre ss pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an unused semaphore, a one will appear at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to 1 for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port immediately owns the semaphore after the left port releases it. ta b l e 5 shows sample semaphore operations. when reading a semaphore, all eight or nine data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. initialization of the semaphore is not automatic and must be reset during initialization program at power-up. all semaphores on both sides should have a 1 written into them at initialization from both sides to assure that they are free when needed. [+] feedback
cy7c138 document #: 38-06037 rev. *g page 15 of 21 table 3. non-contending read/write inputs outputs operation ce r/w oe sem i/o 0-7 h x x h high z power-down h h l l data out read data in semaphore x x h x high z i/o lines disabled h x l data in write to semaphore l h l h data ut read l l x h data in write l x x l illegal condition table 4. interrupt operation example (assumes busy l =busy r =high) left port right port function r/w ce oe a 0-11 int r/w ce oe a 0-11 int set left int x x x x l l l x ffe x reset left int x l l ffe h x x x x x set right int l l x fff x x x x x l reset right int x x x x x x l l fff h table 5. semaphore operation example function i/o 0-7 left i/o 0-7 right status no action 1 1 semaphore free left port writes semaphore 0 1 left port obtains semaphore right port writes 0 to semaphore 0 1 right side is denied access left port writes 1 to semaphore 1 0 right port is granted access to semaphore left port writes 0 to semaphore 1 0 no change. left port is denied access right port writes 1 to semaphore 0 1 left port obtains semaphore left port writes 1 to semaphore 1 1 no port accessing semaphore address right port writes 0 to semaphore 1 0 right port obtains semaphore right port writes 1 to semaphore 1 1 no port accessing semaphore left port writes 0 to semaphore 0 1 left port obtains semaphore left port writes 1 to semaphore 1 1 no port accessing semaphore [+] feedback
cy7c138 document #: 38-06037 rev. *g page 16 of 21 figure 15. typical dc and ac characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 ?55 25 125 1.2 1.0 120 80 0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized supply current vs. ambient temperature ambient temperature (c) output voltage (v) output source current vs. output voltage 0.0 0.8 0.8 0.6 0.6 normalized i cc , i sb v cc = 5.0 v v in = 5.0 v 0 i cc 1.6 1.4 1.2 1.0 0.8 ?55 125 normalized t aa normalized access time vs. ambient temperature ambient temperature (c) 1.4 1.3 1.2 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage v cc = 5.0 v 0.6 0.8 1.25 1.0 0.75 10 normalized i cc 0.50 normalized i cc vs. cycle time cycle frequency (mhz) 1.00 0.25 0 1.0 2.0 3.0 5.0 normalized t pc 25.0 30.0 20.0 10.0 5.0 0 200 400 600 800 delta t aa (ns) 0 15.0 0.0 supply voltage (v) typical power-on current vs. supply voltage capacitance (pf) typical access time change vs. output loading 4.0 1000 0.50 28 0.2 0.6 1.2 i sb3 normalized i, cc i sb 0.2 0.4 25 1.1 5.0 t a = 25 c 40 160 200 5.0 40 66 0.75 i cc i sb3 v cc = 5.0 v t a = 25 c t a = 25 c v cc = 5.0 v v cc = 4.5 v t a = 25 c t a = 25 c v cc = 5.0 v v in = 5.0 v v in = 5.0 v [+] feedback
cy7c138 document #: 38-06037 rev. *g page 17 of 21 ordering information ordering code definition 4k x8 dual-port sram speed (ns) ordering code package diagram package type operating range 25 CY7C138-25JXC 51-85005 68-pin plastic leaded chip carrier (pb-free) commercial cy7c138-25jxi 51-85005 68-pin plastic leaded chip carrier (pb-free) industrial temperature range: x = c or i c = commercial; i = industrial package: j = plcc x=x:pb-free (rohs compliant) xx = speed = 25 ns density: 138 = part number identifier cy7c = cypress dual port srams xxx cy7c - xx xx x [+] feedback
cy7c138 document #: 38-06037 rev. *g page 18 of 21 package diagram figure 16. 68-pin plastic leaded chip carrier (51-85005) 51-85005 *b [+] feedback
cy7c138 document #: 38-06037 rev. *g page 19 of 21 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor tqfp thin quad plastic flatpack i/o input/output sram static random access memory plcc plastic leaded chip carrier ttl transistor transistor logic symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes ? ohms mv milli volts mhz mega hertz pf pico farad wwatts c degree celcius [+] feedback
cy7c138 document #: 38-06037 rev. *g page 20 of 21 document history page document title: cy7c138 4k x 8/9 dual-port static ram with sem, int, busy document number: 38-06037 rev. ecn no. orig. of change submission date description of change ** 110180 szv 09/29/01 change from spec number: 38-00536 to 38-06037 *a 122287 rbi 12/27/02 power-up requirements added to maximum ratings information *b 393403 yim see ecn added pb-free logo added pb-free parts to ordering information: cy7c138-15jxc, CY7C138-25JXC, cy7c139-25jxc *c 2623658 vkn/pyrs 12/17/08 added cy7c138-25jxi part removed cy7c139 from the ordering information table *d 2672737 gnkk 03/12/2009 corrected title in the document history table *e 2714768 vkn/aesa 06/04/2009 corrected defective logic block diagram, pinouts and package diagrams *f 2898564 rame 03/24/10 removed inactive parts. updated package diagram. *g 3099184 admu 12/02/2010 removed information for cy7c139 parts. removed speed bins -15,-35,-55. updated datasheet as per new template added acronyms and units of measure table added ordering code definition updated all footnotes. [+] feedback
document #: 38-06037 rev. *g revised december 2, 2010 page 21 of 21 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c138 ? cypress semiconductor corporation, 2009-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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